Sizing Analog CMOS Circuits
Cagliari, May 16 - 18, 2007
Instructor: Prof. Paul G. A. Jespers - Université Catholique de Louvain la Neuve (BE)
Duration: 9 hours (3 hours/day)
Venue: DIEE - University of Cagliari - Aula B1 (Day 1-2) - Lab "Venezia" (Day 3)
The design of analog parts, like Op. Amps, requires fixing transistor geometries and bias conditions in order to meet pre-defined objectives. Mostly, this is done by taking advantage of repeated trimming simulations. Sizing methodologies like the so-called gm/ID methodology supplement the process. The technique is applied to the intrinsic gain stage to begin with. One makes use of a semi-empirical transistor model derived from the EKV model. Parameter acquisition is described briefly and a number of verifications are carried out to prove the capacity of the model to represent correctly DC characteristics of sub-micron devices operating under low-power low-voltage conditions. Following this, the methodology is put to use in order to size a Miller Op. Amp, which attains a given gain-bandwidth product, requires minimal power consumption and achieves an acceptable phase margin. All the examples that are considered take advantage of a custom MATLAB toolbox that will be available during the practical session ending the course.
Wednesday 16th May 2007, 14:00-17:00, Aula B1
Thursday 17th May 2007, 14:00-17:00, Aula B1
Friday 18th May 2007, 14:00-17:00, Lab. "Venezia"
Luigi RAFFO (luigi at diee.unica.it)
Massimo BARBARO (barbaro at unica.it)