DRIEI - Dottorato di Ricerca in Ingegneria Elettronica e Informatica
Università di Cagliari, Italy

Short Course

Advanced Microelectronic Design
Cagliari, June 11 - 13, 2008


Instructor: Prof. Paul G. A. Jespers - Université Catholique de Louvain la Neuve (BE)
P. G. A. Jespers is Prof Emeritus of the Université Catholique de Louvain, Louvain-la-Neuve, Belgium where he was the head of the Microelectronics Division for more than 20 years. His main interest is in Analog Integrated Circuits. He has been visiting professor at the University of California, Berkeley, UFRGS, Porto Alegre, UCC, Cordoba, and the E. Cowan Univertsity, Perth. He is currently involved in education programs in France and Italy. He is the author of a recent book on integrated converters published by Oxford University Press. Prof. Jespers is an IEEE fellow.

Duration: 15 hours (3 days)
Language: English
Venue: DIEE - University of Cagliari - Aula B0* (Day 1-2) - Lab "Venezia"* (Day 3)
Contact: Massimo BARBARO (barbaro SUBSTITUTE_AT unica.it)
*WARNING: The classroom may change due to logistics reasons, please visit this page a few days before the course to verify the exact location.
Acknoledgement: The course has been organized within the Visiting Professors Initiative of University of Cagliari, funded by "Regione Autonoma della Sardegna"

SCHEDULE
Day 1 (Wednesday, 11 June 2008, DIEE Pad. A, Aula Mocci (DIEE-A First Floor) *)
Integrated Converters
09:00-12:00

1) Evaluation techniques
Static : INL and DNL. Dynamic: CDT, SNR, ENOB. Bandwidth.
2) Parallel D to A converters.
Organization: binary vs. thermometric. Statistical averaging. Basic architectures: (a) R2R, MOS-R2R. (b) binary weighted unit-capacitors, parasitics, (c) transistor arrays, minimization of systematic mismatch. Segmented converters.
3) Flash A to D converters .
Challenges: area, power consumption, offsets, input capacitance, time skew, non-linear distortion, metastability. Offset averaging. Folding converters .

14:00-17:00

4) Multistep A to D converters.
Architectures: subranging, recycling and pipeline. Error sources and corrections: Transition position errors and digital correction. Transition magnitude errors, even vs. odd quantization levels, floating point converter. Interstage gain. The I.5-bit stage. Background calibration. Implementations.
5) Delta Sigma converters.
The basic idea: Exchange time for magnitude resolution (embedded systems). A to D conv: Oversampling and noise shaping, Linear and non-linear analysis. Decimation steps. Noise shaper impairments: single-bit vs. multibit D to A. Randomization. Dynamic range. Stability. Mash converters. Synthesis. D to A conv : Principles. Interpolation steps.

Day 2 (Thursday, 12 June 2008, DIEE Pad. A, Aula Mocci (DIEE-A First Floor) *)
gm/ID sizing methodology for low-power/voltage CMOS circuits
09:00-12:00
1) Gain-bandwidth sizing methodology of the intrinsic gain stage.
Strong and weak inversion models. E.K.V. model. gm/ID methodology .
2) Sizing the short channel intrinsic gain stage.
Empirical gm/ID sizing methodology. Gradual channel Charge Sheet and E.K.V. gm/ID’s. Simple or advanced models? Requirements. Assumptions. An E.K.V. variable parameters model. Param identification. Sensitivity to threshold voltage roll-off, channel length modulation, D.I.B.L. . gm/ID sizing with variable param. E.K.V. model. Impact of transistor partitioning and parasitics. gd/ID for gain evaluation. Global optimization. Implementation.
14:00-17:00
3) Sizing the basic Miller Op. Amp.
Preliminary analysis. Poles and zeros. 1st and 2d order constraints. 2-D gm/ID sizing methodology and optimization. From Miller to single stage Op. Amp.
4) Sizing the basic cascode Op. Amp.
2-D gm/ID sizing methodology and optimization. Gain boosting. Minimization of the impact of the doublet.
Day 3 (Friday, 13 June 2008, Lab "Venezia"*)
09:00-12:00

ADCs: Hands-on system-level simulation session.

  • Impact of unit-elements errors on INL and DNL of Parallel D to A converters vs. organization.
  • CDT test of flash converter.
  • Waveforms of cyclic A to D multistep converters. Spectral signature. SNR plot. ENOB.
  • Delta Sigma A to D. Noise shaper waveforms. Spectrum. Impact of quantizer resolution. Randomization. SNR plot. ENOB.
  • Delta Sigma D to A. Waveforms. Spectrum.

Sizing Methodology: Hands-on system-level simulation session.  

  • Sizing the intrinsic gain stage vs. gain-bandwidth specs.
  • Sizing the Miller Op. Amp. to fulfil gain-bandwidth or/and slew-rate specs aiming at min power consumption and/or area, large gain.
  • Miscellaneous.