DRIEI - Dottorato di Ricerca in Ingegneria Elettronica e Informatica
Università di Cagliari, Italia

Ph.D. Course
Advanced Digital Implementation Flow
Cagliari, January XX-YY, 2010

Course Advanced Digital Implementation Flow
Credits 3 credits, 24 hours (4 days)
Instructor Massimo Barbaro
Language Italian (English on request of attendants)
Venue DIEE, University of Cagliari - Classroom: Laboratorio Didattico (DIEE Pad. B)
Contact Massimo BARBARO (barbaro SUBSTITUTE_AT unica.it), Tel. 0706755770
Evaluation Test and final project.

WARNING: The classroom and exact dates may change due to logistics reasons, please visit this page a few days before the course to verify the exact location.
Acknoledgements: During this course, state-of-the-art EDA/CAD software will be made available to students thanks to Cadence University Software Program (managed, for Europe, by Europractice) and thanks to students' funding (ex art. 5)

Last Update: 21-Jul-2009 11:56


Laboratorio Didattico - DIEE Pad. B
Laboratorio Didattico - DIEE Pad. B
Laboratorio Didattico - DIEE Pad. B
Laboratorio Didattico - DIEE Pad. B
The scaling of transistors feature size predicted by Moore's law has led to CMOS processes with gate lengths of 90nm and below. Starting from the 90nm technology node, anyway, a number of second-order effects in transistor behavior has emerged and began to play a major role. New issues such as gate leakage, power consumption, mismatch are now leading the design process, especially in the digital domain. The participants will get familiar with the changes introduced in the IC design flows for advanced deep-submicron technology nodes. The 90 nm technology will be the baseline for the EDA-platform used, using relevant process parameters and IP-libraries. The course will create a deeper understanding of the issues involved. The course will also build hands-on experience. State-of-the-art EDA tools and relevant design exercises will get the participants to a level to build a bridge towards changing and updating the design flow for future challenges introduced by the 65 nm and 45 nm process characteristics and constraints.

Design Environment And Tool Chain
Introduction to90nm digital IC design. (Technology Changes,Design and Verification, Test Strategy, Low Power Techniques,Physical Implementation and Signoff Technologies) - 90nm EDA tools and implementation flows
Design Synthesis
Modern synthesis technologies: topographical synthesis (with physical constraints), low power optimisation (both static and dynamic power), and Scan Test (with compressed scan). Design techniques to contribute to the leakage reduction by combining techniques and materials on several fronts.
Design Planning And Floorplanning
Floorplanning & power network implementation and analysis including IR drop and electro migration analysis. Multi Voltage and Low Power requirements impact design hierarchy and power grid and necessitate the introduction of Voltage Islands, Isolation Cells, MTCMOS. Library analysis and management (standard cells, IOs, memory). IP Integration and management (hard-, soft-, analog IP)
Low-power Flow
Dynamic & leakage power minimization and how to use a unified power intent specification to assure coherence over the design flow and to allow verification of the power features. This includes always on buffer/register usage.
Physical synsthesis
How do we move from a the synthesized gate level description and floorplan to a physical hierarchy and how do we deal with Hard Macro’s in such a Hierarchical and MultiVoltage design. Multiple clock tree synthesis. Design for test. Multimode and multicorner. Routing to GDS2. IR drop analysis. Signoff. Tapeout.