DRIEI - Dottorato di Ricerca in Ingegneria Elettronica e Informatica
Università di Cagliari, Italia

Ph.D. Course
Advanced Analog Implementation Flow
Cagliari, September 22-25, 2009

Course Advanced Analog Implementation Flow
Credits 3 credits, 24 hours (4 days)
Instructor Massimo Barbaro
Language Italian (English on request of attendants)
Venue DIEE, University of Cagliari - Classroom: Laboratorio Didattico (DIEE Pad. B)
Contact Massimo BARBARO (barbaro SUBSTITUTE_AT unica.it), Tel. 0706755770
Evaluation Test and final project.

WARNING: The classroom may change due to logistics reasons, please visit this page a few days before the course to verify the exact location.
Acknoledgements: During this course, state-of-the-art EDA/CAD software will be made available to students thanks to Cadence University Software Program (managed, for Europe, by Europractice) and thanks to students' funding (ex art. 5)

Last Update: 20-Jul-2009 16:38
Schedule

Day

Hour
Classrom
Tuesday 22/09/2009
09:00-12:00 and 15:00-18:00
Laboratorio Didattico - DIEE Pad. B
Wednesday 23/09/2009
09:00-12:00 and 15:00-18:00
Laboratorio Didattico - DIEE Pad. B
Thursday 24/09/2009
09:00-12:00 and 15:00-18:00
Laboratorio Didattico - DIEE Pad. B
Friday 25/09/2009
09:00-12:00 and 15:00-18:00
Laboratorio Didattico - DIEE Pad. B
Goal
The scaling of transistors feature size predicted by Moore's law has led to CMOS processes with gate lengths of 90nm and below. Starting from the 90nm technology node, anyway, the traditional approach to CMOS analog design has proven to be suffering for the deep changes in transistor behavior. In order to be able to move to deep submicron technologies, the analog circuit designer must handle a number of new issues This course will provide a short overview of the 90nm IC process flow, it will cover modelling issues, hand calculation versus simulation accuracy, transistor level and behavioral level design, analog cell trimming using digital functions, mixed mode simulation, mismatch and yield modelling and analysis, and analog modelling and circuit optimisation.

Syllabus
Technology aspects in 90nm analog processes
Overview of a typical 90nm process-flow - Differences between previous CMOS generations and 90nm - Active, poly and metal tiling - Uniform metal density - Impact of metal tiling and cheesing on inductors design
Modeling Issues
Specific 90nm physical effects (DIBL, gate current, mobility saturation, velocity saturation) - Pinch-off surface potential and inversion factor parameter - Threshold voltage and slope factor - gm/Id and intrinsic gain behaviour - CV modeling - Noise modeling - Gate leakage
Evaluation versus simulation
Approximations for hand calculations - Parameter extraction flow for hand calculation at 90nm node - Simulation issues (accuracy, corners) - Optimization flow strategies - Design verification and fine-tuning
Transistor Level And Behavioural Level Design
Structured analog design flow - Basic analog structures library - Design trade-offs on the level of basic analog structures - Design sequence and procedural design flow
Analog Cells Trimming Using Digital Functions
Calibration principle - Detection of imperfections - Compensation of imperfections - Calibration elements (DAC & algorithm) - Calibration loop modeling - Integration in the convential simulation flow
Mismatch And Yield Modelling And Analysis
Mismatch and variability analysis (physical phenomena, models, comparisoon to older technologies, layout issues) - Techniques for yield and mismatch analysis - Signal integraty (substrate noise evaluation, power supply noise evaluation, noise rduction and shielding techniques)

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