Schedule: 
Lecture 1 (3 hours): Monday,
July 4, 1013
Lecture 2 (3 hours): Monday,
July 4, 1417
Lecture 3 (3 hours): Tuesday,
July 5, 1013
Lecture 4 (3 hours): Tuesday,
July 5, 1417
Lecture 5 (3 hours): Wednesday,
July 6, 1013
Lecture 6 (3 hours): Wednesday,
July 6, 1417
Lecture 7 (3 hours): Thursday,
July 7, 1013
Lecture 8 (3 hours): Thursday,
July 7, 1417

Topics: 
Integrated converters (6 hours course + 2 hours Matlab simulations).
 Basic concepts (INL, DNL, quantization noise,...). Evaluation techniques, CDT, FFT, ENOB, figure of merit. Bandwidth.
 Single clock cycle D to A converters. Principles. INL and DNL of binary organized blocs making use of unary charge packets, unary currents, or thermometric architectures. Error compensation techniques (first and second order). Highspeed D to A converters. Segment converters.
 A to D converters. Anti aliasing. Serial and parallel (flash) architectures. Speedareapower challenges. Compensation techniques.
 Multistep A to D converters.The quantization block. Architectures (recycling, pipelined). Principal error sources and compensation techniques. The 1.5 bit converter stage. Background correction.
 DeltaSigma A to D converters. Oversampling and noiseshaping. Order. Number of quantization bits. Decimation. Sources of impairments and compensation techniques. Examples. Mash converters. D to A DeltaSigma converters.
 Matlab lab sessions illustrate the principles of the D to A and A to D converters by means of simulation files. The impact of impairments on converter performances and the benefit from compensation techniques can be tested.
Sizing lowpower low voltage CMOS analog amplifiers by means of the gm/ID methodology. (12 hours course + 2 x 2 hours Matlab simulations).
 The generic Op. Amp. The Intrinsic Gain Stage (IGS). Analysis. A large signal model needed for sizing: quadratic (strong inversion only), subthreshold (weak inversion only), compact or semiempirical (all modes of operation). CMOS analog circuits take increasingly advantage of large transistors operating in the moderate inversion region to enhance gain and lower power consumption even at high frequencies.
 The gm/ID sizing method. How to optimize several objectives while meeting concurrently a set of specifications: e.g. minimal power consumption and a given gainbandwidth product.
 A compact large signal model: the EKV1 model, an approximation of the gradual channel Charge Sheet Model (CSM). Short survey of physical background. Parameter extraction and drain current reconstruction. Examples. Sizing a long channel IGS.
 Short channel effects (threshold voltage drop, DIBL, Early effect, mobility degradation). Semiempirical gm/ID sizing of the IGS based on lookup tables derived from advanced models (BSIM,PSP).
 An extension of the EKV1 compact model for shortchannel devices making use of bias dependent parameters. Parameter acquisition and drain current reconstruction. Short channel effects impact on the parameters.
 Comparison of sizing methods based on the semiempirical and compact model approaches considering a submicron IGS in moderate inversion that achieves a given gainbandwidth product. Impact of extrinsic capacitances and mobility degradation.
 The Miller Op.Amp. Analysis (poles and zeros, pole splitting, phase margin). Gainbandwidth sizing strategy based on polezero specifications making use of a 2dimensional expansion of the gm/ID methodology aiming at multiple objectives (annihilate systematic offset, compromise gain, power consumption and area).
 The single stage Op. Amp, a hidden Miller Op. Amp.
