PhD Seminar Course on

Design techniques for integrated front-end electronics

Cagliari, July 4-7, 2011

This activity was made possible by the "Visiting Professors 2010" program of the University of Cagliari, sponsored by the Autonomous Region of Sardinia
Instructor: Paul Jespers
Duration: 24 hours

Lecture 1 (3 hours):     Monday,         July 4,    10-13

Lecture 2 (3 hours):     Monday,         July 4,    14-17

Lecture 3 (3 hours):     Tuesday,        July 5,    10-13

Lecture 4 (3 hours):     Tuesday,        July 5,    14-17

Lecture 5 (3 hours):     Wednesday,  July 6,    10-13

Lecture 6 (3 hours):     Wednesday,  July 6,    14-17

Lecture 7 (3 hours):     Thursday,       July 7,    10-13

Lecture 8 (3 hours):     Thursday,       July 7,    14-17

Venue: B1 Classroom (DIEE building B)
Topics: Integrated converters (6 hours course + 2 hours Matlab simulations).
  • Basic concepts (INL, DNL, quantization noise,...). Evaluation techniques, CDT, FFT, ENOB, figure of merit. Bandwidth.
  • Single clock- cycle D to A converters. Principles. INL and DNL of binary organized blocs making use of unary charge packets, unary currents, or thermometric architectures. Error compensation techniques (first and second order). High-speed D to A converters. Segment converters.
  • A to D converters. Anti aliasing. Serial and parallel (flash) architectures. Speed-area-power challenges. Compensation techniques.
  • Multistep A to D converters.The quantization block. Architectures (recycling, pipelined). Principal error sources and compensation techniques. The 1.5 bit converter stage. Background correction.
  • Delta-Sigma A to D converters. Oversampling and noise-shaping. Order. Number of quantization bits. Decimation. Sources of impairments and compensation techniques. Examples. Mash converters. D to A Delta-Sigma converters.
  • Matlab lab sessions illustrate the principles of the D to A and A to D converters by means of simulation files. The impact of impairments on converter performances and the benefit from compensation techniques can be tested.
Sizing low-power low voltage CMOS analog amplifiers by means of the gm/ID methodology. (12 hours course + 2 x 2 hours Matlab simulations).
  • The generic Op. Amp. The Intrinsic Gain Stage (IGS). Analysis. A large signal model needed for sizing: quadratic (strong inversion only), subthreshold (weak inversion only), compact or semi-empirical (all modes of operation). CMOS analog circuits take increasingly advantage of large transistors operating in the moderate inversion region to enhance gain and lower power consumption even at high frequencies.
  • The gm/ID sizing method. How to optimize several objectives while meeting concurrently a set of specifications: e.g. minimal power consumption and a given gain-bandwidth product.
  • A compact large signal model: the EKV-1 model, an approximation of the gradual channel Charge Sheet Model (CSM). Short survey of physical background. Parameter extraction and drain current reconstruction. Examples. Sizing a long channel IGS.
  • Short channel effects (threshold voltage drop, DIBL, Early effect, mobility degradation). Semi-empirical gm/ID sizing of the IGS based on look-up tables derived from advanced models (BSIM,PSP).
  • An extension of the EKV-1 compact model for short-channel devices making use of bias dependent parameters. Parameter acquisition and drain current reconstruction. Short channel effects impact on the parameters.
  • Comparison of sizing methods based on the semi-empirical and compact model approaches considering a submicron IGS in moderate inversion that achieves a given gain-bandwidth product. Impact of extrinsic capacitances and mobility degradation.
  • The Miller Op.Amp. Analysis (poles and zeros, pole splitting, phase margin). Gain-bandwidth sizing strategy based on pole-zero specifications making use of a 2-dimensional expansion of the gm/ID methodology aiming at multiple objectives (annihilate systematic offset, compromise gain, power consumption and area).
  • The single stage Op. Amp, a hidden Miller Op. Amp.
Organizer: Massimo Barbaro
Dep. of Electrical and Electronic Engineering
University of Cagliari, Italy
Email: barbaro*REMOVE*